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CY2037
High - Accuracy EPROM Programmable PLL Die for Crystal Oscillators
Features
* EPROM-programmable die for in-package programming of crystal oscillators * High resolution PLL with 12-bit multiplier and 10-bit divider * EPROM-programmable capacitor tuning array with Shadow register * Twice programmable die (CY2037A, CY2037B[1] and CY2037-2). * Simple 4-wire programming interface * On-chip oscillator runs from 10-30 MHz fundamental tuned crystal * EPROM-selectable TTL or CMOS duty cycle levels * Operating frequency -- 1-133 MHz at 5V -- 1-100 MHz at 3.3V * * * * -- 1-66.6 MHz at 2.7V Sixteen selectable post-divide options, using either PLL or reference oscillator output Programmable power down (PD#) or OE pin (CY2037A, CY2037B, and CY2037-2) Frequency Select (CY2037-3) Programmable asynchronous or synchronous OE and power down (PD#) modes (CY2037A, CY2037B and CY2037-2) Low Jitter outputs typically -- < 100 ps (pk-pk) at 5V and f>33 MHz -- < 125 ps (pk-pk) at 3.3V and f>33 MHz * 3.3V or 5V operation * Small Die * Controlled rise and fall times and output slew rate Table 1. Device Functionality: Output Frequencies Parameter Fo Description Output frequency Condition VDD = 4.5V-5.5V VDD = 3.0V-3.6V VDD = 2.7V-3.0V Min. 1 1 1 Max. 133 100 66 Unit MHz MHz MHz
Benefits
* Enables quick turnaround of custom oscillators * Lowers inventory costs through stocking of blank parts * Enables synthesis of highly accurate and stable output clock frequencies with zero or low PPM * Enables fine-tuning of output clock frequency by adjusting CLoad of the crystal * Enables reprogramming of programmed part, to correct errors, and control excess inventory * Enables programming of output frequency after packaging * Lowers cost of oscillator as PLL can be programmed to a high frequency using a low-frequency, low-cost crystal * Duty cycle centered at 1.4V or VDD/2 * Provides flexibility to service most TTL or CMOS applications * Services most PC, networking, and consumer applications * Provides flexibility in output configurations and testing * Enables low-power operation or output enable function * Enables two frequency options for meeting different industry standards, i.e., PAL/NTSC * Provides flexibility for system applications, through selectable instantaneous or synchronous change in outputs * Suitable for most PC, consumer, and networking applications * Lowers inventory cost as same die services both applications * Enables encapsulation in small-size, surface mount packages * Has lower EMI than oscillators
*
Note 1. The CY2037A and CY2037B are identical. However, the CY2037B is recommended for all new designs
Cypress Semiconductor Corporation Document #: 38-07354 Rev. *D
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised February 26, 2007
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CY2037
Logic Block Diagram
PD#/OE or FS
XG XD
CRYSTAL OSCILLATOR
HIGH ACCURACY PLL
CONFIGURATION EPROM
MUX
/ 1, 2, 4, 8, 16, 32, 64, 128
CLKOUT
Die Pad Description
H o r iz o n ta l s c r ib e
VDD VDD XX
CLKO UT N /C
V e r tic a l s c r ib e
XD N /C XR XG P D # /O E o r F S
Y
D e v ic e N a m e
Note: Active Die Size: X = 55.9 mils / 1420.1 m
Scribe: X (horizontal)= 2.6 mils / 65.6 m Y (vertical)= 3.0 mils / 76.9 m Bond pad opening: 85 m x 85 m Pad pitch: 125 m x 125 m (Pad center to pad center)
VSS VSS
X
Die Pad Summary
Name VDD VSS XD XX XG PD#/OE or FS CLKOUT N/C Die Pad 1,2 8,9 4 3 6 7 Voltage supply Ground Crystal connection. No Connect
[2]
Description
X Coordinate (m) 124.7 1291.35 124.7 124.7 124.7 124.7
Y Coordinate (m) 855.6 , 731 99.6 , 225.2 481.8 606.4 232.6 108
Crystal connection. CY2037A, CY2037B, and CY2037-2--EPROM programmable power down or output enable pad. CY2037-3--Frequency Select. Serves as VPP in programming mode for all devices. Clock output. Also serves as three-state input during programming. No Connect. (Do not bond to these pads)
11 5,10
1282.45 124.7,1282.45
901.8 357.2, 769.4
Note 2. For Customers not bonding the XD or XG pad to external pins, an alternative bonding option would be shorting the Xx pad to the XD pad
Document #: 38-07354 Rev. *D
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CY2037
Functional Description
The CY2037 is an EPROM programmable, high accuracy, PLL-based die designed for the crystal oscillator market. The die attaches directly to a low-cost 10-30 MHz crystal and can be packaged into 4-pin through-hole or surface mount packages. The oscillator devices can be stocked as blank parts and custom frequencies programmed in-package at the last stage before shipping. This enables fast-turn manufacture of custom and standard crystal oscillators without the need for dedicated, expensive crystals. The CY2037 contains an on-chip oscillator and a unique oscillator tuning circuit for fine-tuning of the output frequency. The crystal Cload can be selectively adjusted by programming a set of seven EPROM bits. This feature can be used to compensate for crystal variations or to obtain a more accurate synthesized frequency. The CY2037 uses EPROM programming with a simple 2-wire, 4-pin interface that includes VSS and VDD. Clock outputs can be generated up to 133 MHz at 5V or up to 100 MHz at 3.3V. The entire configuration can be reprogrammed one time, allowing programmed inventory to be altered or reused. The CY2037 PLL die has been designed for very high resolution. It has a 12-bit feedback counter multiplier and a 10-bit reference counter divider. This enables the synthesis of highly accurate and stable output clock frequencies with zero or low PPM error. The clock can be further modified by eight output divider options of 1, 2, 4, 8, 16, 32, 64, and 128. The divider input can be selected as either the PLL or crystal oscillator output providing a total of sixteen separate output options. For further flexibility, the ouput is selectable between TTL and CMOS duty cycle levels. The CY2037A, CY2037B and CY2037-2 also contain flexible power management controls. These parts include both power down (PD#) and OE features with integrated pull-up resistors. The PD# and OE modes have an additional setting to determine timing (asynchronous or synchronous) with respect to the output signal. When PD# or OE modes are enabled, CLKOUT is pulled low by a weak pull down. The weak pull down is easily overdriven by another active CLKOUT for applications that require multiple CLKOUTs on a single signal path. Controlled rise and fall times, unique output driver circuits, and innovative circuit layout techniques enable the CY2037 to have low jitter and accurate outputs, making it suitable for most PC, networking, and consumer applications. On the other hand, the CY2037-3 contains a frequency select function in place of the power down and output enable modes. For example, consumer products often require frequency compatibility with different electrical standards around the world. With this frequency select feature, a product that incorporates the CY2037-3 could be compatible with both NTSC for North American and PAL for Europe simply by changing the FS line. The twice programmable feature is also absent in the
CY2037-3, because the second EPROM row is now being used for the alternate frequency.
EPROM Configuration Block
Table 2 summarizes the features that are configurable by EPROM. Please refer to the "7C8038x/7C8034X Programming Specification" for further details. The specification can be obtained from your Cypress factory representative.
.
Table 2. EPROM Adjustable Features Adjust Frequency Feedback counter value (P) Reference counter value (Q) Output divider selection Oscillator Tuning (load capacitance values) Duty cycle levels (TTL or CMOS) Power management mode (OE or PD#) Power management timing (synchronous or asynchronous)
PLL Output Frequency
The CY2037 contains a high-resolution PLL with 12-bit multiplier and 10-bit divider.The output frequency of the PLL is determined by the following formula: 2 * (P + 5) F PLL = --------------------------- * F REF (Q + 2) where P is the feedback counter value and Q is the reference counter value. P and Q are EPROM programmable values.
Power Management Features (except CY2037-3)
The CY2037 contains EPROM-programmable PD# and OE functions. If Powerdown is selected, all active circuitry on the chip is shut down when the control pin goes low. The oscillator and PLL circuits must re-lock when the part leaves Powerdown Mode. If Output Enable mode is selected, the output is tri-stated and weakly pulled low when the Control pin goes low. In this mode the oscillator and PLL circuits continue to operate, allowing a rapid return to normal operation when the Control input is deasserted. In addition, the PD# and OE modes can be programmed to occur synchronously or asynchronously with respect to the output signal. When the asynchronous setting is used, the power down or output disable occurs immediately (allowing for logic delays) regardless of position in the clock cycle. However, when the synchronous setting is used, the part waits for a falling edge at the output before the power down or output enable signal is initiated, thus preventing output glitches. In either asynchronous or synchronous setting, the output is always enabled synchronously by waiting for the next falling edge of the output.
Document #: 38-07354 Rev. *D
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CY2037
Crystal Oscillator Tuning Circuit
The CY2037 contains a unique tuning circuit to fine-tune the output frequency of the device. The tuning circuit consists of an array of eleven load capacitors on both sides of the oscillator drive inverter. The capacitor load values are EPROM programmable and can be increased in small increments. As
the capacitor load is increased the circuit is fine-tuned to a lower frequency. The capacitor load values vary from 0.17 pF to 8 pF for a 100:1 total control ratio. The tuning increments are shown in the table below. Please refer to the "7C8038x/7C8034x Programming Specification" for further details.
Figure 1. Crystal Oscillator Tuning Circuit Rf External Crystal
C6
C5
C4
C3
C2
C1
C0
Cgo Cdo
C7
C8
C9
C10
CD6
CD5
CD4
CD3
CD2
CD1
CD0
CD3 CD4 CD5 CD6
CD = EPROM BIT T = TRANSISTOR C = LOAD CAPACITOR
Table 3. Crystal Oscillator Parameter Table. Parameter Rf Description Feedback resistor, VDD = 4.5-5.5V Feedback resistor, VDD = 2.7-3.6V Capacitors have 20% Tolerance Cg Cd C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 Gate capacitor Drain Capacitor Series Cap Series Cap Series Cap Series Cap Series Cap Series Cap Series Cap Series Cap Series Cap Series Cap Series Cap 13 9 0.27 0.52 1.00 0.7 1.4 2.6 5.0 0.45 0.85 1.7 3.3 pF pF pF pF pF pF pF pF pF pF pF pF pF Min. 0.5 1.0 Typ. 2 4 Max. 3.5 9.0 Unit M M
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CY2037
Difference Between CY2037A/CY2037B and CY2037-2
The CY2037A/CY2037B contains a shadow register in addition to the EPROM register. The shadow register is an exact copy of the EPROM register and is the default register when the Valid bit is not set. It is useful when the prototype or production environment calls for measuring and adjusting the CLKOUT frequency numerous times. Multiple adjustments can be performed with the shadow register. Once the desired frequency is achieved the EPROM register is permanently programmed.
Some production flows do not require the use of the shadow register. If this is the case, then the CY2037-2 is the device of choice. The CY2037-2 has a disabled shadow register. The CY2037-3 contains the shadow register.
Frequency Select Feature of CY2037-3
The CY2037-3 contains a frequency select function in place of the powerdown and the output enable functions. With the frequency select feature, customers can switch two different frequencies that are configured in the two EPROM rows. The definition of the Frequency Select pin (FS) is Table 4.
Table 4. Frequency Select Pin Decoding for CY2037-3 FS Pin 0 1 . From EPROM Row 0 Configuration From EPROM Row 1 Configuration Output Frequency
Document #: 38-07354 Rev. *D
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CY2037
Absolute Maximum Ratings[3]
Supply Voltage ..................................................-0.5 to +7.0V Input Voltage .............................................. -0.5V to VDD+0.5
Storage Temperature (Non-Condensing).... 55C to +150C Junction Temperature ................................. -40C to +100C Static Discharge Voltage........................................... > 2000V (per MIL-STD-883, Method 3015)
Operating Conditions
Parameter VDD TAJ [4] CTTL Supply Voltage (3.3V) Supply Voltage (5.0V) Operating Temperature, Junction Max. Capacitive Load on outputs for TTL levels VDD = 4.5-5.5V, Output frequency = 1-40 MHz VDD = 4.5-5.5V, Output frequency = 40-133 MHz Max. Capacitive Load on outputs for CMOS levels VDD = 4.5-5.5V, Output frequency = 1-66.6MHz VDD = 4.5-5.5V, Output frequency = 66.6-133MHz VDD = 3.0-3.6V, Output frequency = 1-40 MHz VDD = 3.0-3.6V, Output frequency = 40-100 MHz VDD = 2.7-3.0V, Output frequency = 1-66 MHz Reference Frequency, input crystal. Fundamental tuned crystals only. Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 10 0.05 Description Min. 2.7 4.5 -10 Max. 3.6 5.5 +100 50 25 50 25 30 15 15 30 50 Unit V V C pF pF pF pF pF pF pF MHz ms
CCMOS
XREF tPU
Electrical Characteristics Over the Operating Range (Part was characterized in a 20-pin SOIC package with external
crystal, Electrical Characteristics may change with other package types.) Parameter VIL VIH VOL VOHCMOS VOHTTL IIL IIH IDD IDDS[5] RUP Description Low-level Input Voltage High-level Input Voltage Low-level Output Voltage High-level Output Voltage, CMOS levels High-level Output Voltage, TTL levels Input Low Current Input High Current Power Supply Current, Unloaded Stand-by current Input Pull-up Resistor Test Conditions VDD = 4.5V-5.5V VDD = 2.7V-3.6V VDD = 4.5V-5.5V VDD = 2.7V-3.6V VDD = 4.5V-5.5V, IOL= 16 mA VDD = 2.7V-3.6V, IOL= 8 mA VDD = 4.5V-5.5V, IOH = -16 mA VDD = 2.7V-3.6V, IOH = -8 mA VDD = 4.5V-5.5V, IOH = -8 mA VIN = 0V VIN = VDD VDD = 4.5V-5.5V, Output frequency <= 133MHz VDD = 2.7V-3.6V, Output frequency <= 100 MHz VDD = 2.7V-3.6V VDD = 4.5V-5.5V, VIN = 0V VDD = 4.5V-5.5V, VIN = 0.7VDD 1.1 50 10 3.0 100 20 VDD - 0.4 VDD - 0.4 2.4 10 5 45 25 50 8.0 200 2.0 0.7VDD 0.4 0.4 Min. Typ. Max. 0.8 0.2VDD Unit V V V V V V V V V A A mA mA A M k A
IOE_CLKOUT CLKOUT Pull-down current VDD = 5.0
Notes 3. Stresses greater than listed may impair the life of the device. 4. This product is sold in die form so operating conditions are specified for the die, or junction temperature 5. If external reference is used, it is required to stop the reference (set reference to LOW) during power down
Document #: 38-07354 Rev. *D
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CY2037
Output Clock Switching Characteristics Over the Operating Range[6]
Parameter t1w Description Output Duty Cycle at 1.4V, VDD = 4.5-5.5V t1w = t1A / t1B Output Duty Cycle at VDD/2, VDD = 4.5-5.5V t1x = t1A / t1B Output Duty Cycle at VDD/2, VDD = 3.0-3.6 t1y = t1A / t1B Output Duty Cycle at VDD/2, VDD = 2.7-3.0 t1y = t1A / t1B Test Conditions 1-40 MHz, CL <=50 pF 40-66 MHz, CL <=15 pF 66-125 MHz, CL <=25 pF 125-133 MHz, CL <=15 pF 1-66.6 MHz, CL <=25 pF 66.6-125 MHz, CL <=25 pF 125-133 MHz, CL <=15 pF 1-40 MHz, CL <=30 pF 40-100 MHz, CL <=15 pF 1-40 MHz, CL <=15 pF 40-66.6 MHz, CL <=10 pF Min. 45 45 40 40 45 40 40 45 40 40 40 Typ. Max. 55 55 60 60 55 60 60 55 60 60 60 1.8 1.2 0.9 3.4 4.0 2.4 1.8 1.2 0.9 3.4 4.0 2.4 1 T/2 10 1 T/2 10 T 2 T+10 15 2 T+10 15 1.5T+2 5 125 200 1% of FO Unit % % % % % % % % % % % ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ms ns ns ns
t1x
t1y
t1z
t2
Output Clock Rise Time Between 0.8V-2.0V, VDD = 4.5V-5.5V, CL = 50 pF Between 0.8V-2.0V, VDD = 4.5V-5.5V, CL = 25 pF Between 0.8V-2.0V, VDD = 4.5V-5.5V, CL = 15 pF Between 0.2VDD-0.8VDD, VDD = 4.5V-5.5V, CL = 50 pF Between 0.2VDD-0.8VDD, VDD = 3.0V-3.6V, CL = 30 pF Between 0.2VDD-0.8VDD, VDD = 2.7V-3.6V, CL = 15 pF Output Clock Fall Time Between 0.8V-2.0V, VDD = 4.5V-5.5V, CL = 50 pF Between 0.8V-2.0V, VDD = 4.5V-5.5V, CL = 25 pF Between 0.8V-2.0V, VDD = 4.5V-5.5V, CL = 15 pF Between 0.2VDD- 0.8VDD, VDD = 4.5V-5.5V, CL = 50 pF Between 0.2VDD- 0.8VDD, VDD = 3.0V-3.6V, CL = 30 pF Between 0.2VDD- 0.8VDD, VDD = 2.7V-3.6V, CL = 15 pF PD# pin LOW to HIGH[7]
t3
t4 t5a t5b t6 t7a t7b t8
Start-up Time Out of Power D own
Power Down Delay Time PD# pin LOW to output LOW (synchronous setting) (T = period of Output clk) Power Down Delay Time PD# pin LOW to output LOW (asynchronous setting) Power Up Time Output Disable Time (synchronous setting) Output Disable Time (asynchronous setting) Output Enable Time (always synchronous enable) Peak-to-Peak Period Jitter From power on[7] OE pin LOW to output Hi-Z (T = period of output clk) OE pin LOW to output Hi-Z OE pin LOW to HIGH (T = period of output clk) VDD = 4.5V-5.5V, Fo > 33 MHz, VCO > 100 MHz VDD = 2.7V-3.6V, Fo > 33 MHz, VCO > 100 MHz VDD = 2.7V-5.5V, Fo < 33 MHz
t9
100 125 250
ps ps ps
Notes 6. Not all parameters measured in production testing. 7. Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70 ohms.
Document #: 38-07354 Rev. *D
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CY2037
Switching Waveforms Figure 2. Duty Cycle Timing (t1w, t1x, t1y, t1z)
OUTPUT
t1A
t1B
Figure 3. Output Rise/Fall Time
VDD OUTPUT 0V t2 t3
Figure 4. Power Down Timing (synchronous and asynchronous modes)
POWER DOWN
VDD 0V VIL
VIH t4
CLKOUT (synchronous[8]) T CLKOUT (asynchronous[9]) t5b 1/f t5a 1/f
Figure 5. Power-up Timing
VDD POWER UP CLKOUT 0V
VDD - 10% t6 min. 30 s max. 30 ms
1/f
Notes 8. In synchronous mode the power down or output tri-state is not initiated until the next falling edge of the output clock. 9. In asynchronous mode the power down or output tri-state occurs within 25 ns regardless of position in the ouput clock cycle.
Document #: 38-07354 Rev. *D
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CY2037
]
Ordering Information[10]
Ordering Code CY2037AWAF[11] CY2037-2WAF
[11]
Type Wafer Wafer Wafer Wafer Wafer
Wafer Thickness 14 0.5 mils 14 0.5 mils 14 0.5 mils 14 0.5 mils 11 0.5 mils
Operating Range -10C to +100C -10C to +100C -10C to +100C -10C to +100C -10C to +100C
CY2037-3WAF[11] CY2037BWAF CY2037B-11WAF
Note 10. The only difference between the CY2037A/CY2037B and the CY2037-2 is that the CY2037-2 has the shadow register disabled. The CY2037-3 replaces the power-down options with a Frequency Select, and contains the shadow register. 11. The CY2037B is recommended for all new designs
Document #: 38-07354 Rev. *D
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY2037
Document History Page
Document Title: CY2037 High-Accuracy EPROM Programmable PLL Die for Crystal Oscillators Document Number: 38-07354 REV. ** *A *B *C ECN NO. 112248 121857 291092 522769 Issue Date 03/01/02 12/14/02 See ECN See ECN Orig. of Change DSG RBI RGL RGL Description of Change Change from Spec number: 38-00679 to 38-07354 Power-up requirements added to Operating Conditions Information Updated Min. Operating Temperature, Junction Added CY2037B information. Updated absolute maximum Junction temperature specification. Updated Ordering information table. Added Die Pad description and coordinates Minor Change: To post on web
*D
804376
See ECN
RGL
Document #: 38-07354 Rev. *D
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